The present invention relates to nonvolatile memories with conductive floating gates having an upward protrusion.
A nonvolatile memory cell with a conductive floating gate is operated by changing or sensing a charge on the floating gate. The charge on the floating gate is changed or sensed by means of inducing a voltage on the floating gate. This voltage is induced by means of the capacitive coupling between the floating gate and another gate (e.g. a control gate). In order to reduce the operating voltages in the memory cell, it is desirable to improve the gate coupling ratio which is the ratio of the capacitance between the two gates to the total capacitance associated with the floating gate.
FIG. 1 illustrates a flash memory cell described in U.S. Pat. No. 6,057,575 issued May 2, 2000 to Jenq. The cell is formed in and over a semiconductor substrate 120. Silicon dioxide 130 is thermally grown on substrate 120. Select gate 140 is formed on oxide 130. Silicon dioxide 150 is thermally grown on a region of substrate 120 not covered by the select gate. ONO 154 (a sandwich of a layer of silicon dioxide, a layer of silicon nitride, and a layer of silicon dioxide) is formed on select gate 140. Floating gate 160 is formed on dielectric layers 150154. A portion of floating gate 160 overlies the select gate 140.
ONO layer 164 is formed on the floating and select gates. Control gate 170 is formed on ONO 164. The control gate overlies floating gate 160 and select gate 140.
N+ source and drain regions 174, 178 are formed in substrate 120.
Since the floating gate 160 and the control gate 170 extend over the select gate, the capacitance between the floating and control gates is increased without a corresponding increase in the cell area. The capacitance is increased both due to the horizontal portions of the floating and control gates over the select gate, and due to the vertical portions along the sidewall of the select gates.
In order to reduce the memory array and increase the memory packing density, it is desirable to fabricate the memory using self-aligned processes, i.e. processes less dependent on photolithography. The cell of FIG. 1 can be fabricated by a self-aligned process in which the left and right edges of floating gate 160 and control gate 170 are defined by a single photolithographic mask.